The present invention relates, in general, to chip-scale semiconductor packages and a method of manufacturing such packages and, more particularly, to a chip-scale semiconductor package of the fan-out type and a method of manufacturing such a package, with solder balls of the package being arranged on an external area of a circuit substrate extending outside the edge of a semiconductor chip in addition to the area of the substrate above the chip, the package thus carrying an increased number of solder balls, or the signal input/output terminals, thereon.
As is well known to those skilled in the art, a semiconductor package is a device designed to mount a semiconductor chip on a mother board, in addition to intermediating input/output signals between the chip and the mother board. In accordance with the recent trend of compactness, lightness, thinness and smallness of semiconductor chips, it has been necessary to make such semiconductor packages of a chip size meeting the compactness, lightness, thinness and smallness of the semiconductor chip. Such a chip-sized package is so-called a chip-scale semiconductor package in the art.
FIGS. 11 and 12 show the construction of two types of conventional chip-scale semiconductor packages, respectively.
The package 100xe2x80x2 of FIG. 11 is a conventional chip-scale package of the lead type. As shown in the drawing, the chip-scale package 100xe2x80x2 of the lead type comprises a semiconductor chip 40xe2x80x2, having a plurality of signal input/output pads 41xe2x80x2 on its opposite upper edges or along the square edge. Such pads 41xe2x80x2 are called xe2x80x9cedge padsxe2x80x9d in the art. A flexible circuit substrate 10xe2x80x2 is attached to the upper surface of the chip 40xe2x80x2 by an adhesive layer 21xe2x80x2, except for an area around the signal input/output pads 41xe2x80x2, with the adhesive layer 21xe2x80x2 being uniformly formed between the substrate 10xe2x80x2 and the chip 40 within an area of the substrate 10xe2x80x2. The above substrate 10xe2x80x2 has a plurality of integrated circuit patterns regularly arranged on its polyimide layer 12xe2x80x2. The above circuit patterns, individually comprising a lead 13xe2x80x2, a connector 14xe2x80x2 and a solder ball land 15xe2x80x2, are electrically connected to the signal input/output pads 41xe2x80x2 of the chip 40xe2x80x2 at the leads 13xe2x80x2, respectively. A cover coat 16xe2x80x2 is coated on the top surface of the substrate 10xe2x80x2 in a way such that the coat 16xe2x80x2 opens for both the leads 13xe2x80x2 and the solder ball lands 15xe2x80x2 of the circuit patterns. A solder ball 70xe2x80x2 is welded to each of the solder ball lands 15xe2x80x2 which are exposed through the cover coat 16xe2x80x2. The solder balls 70xe2x80x2 are used for mounting the semiconductor package 100xe2x80x2 on a mother board and as signal input/output terminals of the package 100xe2x80x2. In order to protect both the pads 41xe2x80x2 of the chip 40xe2x80x2 and the leads 13xe2x80x2 of the circuit patterns from the atmospheric environment, the opposite upper edges or the square upper edge of the chip 40xe2x80x2 are individually covered using a packaging material, thus forming a packaging part 60xe2x80x2.
On the other hand, the package 101xe2x80x2 of FIG. 12 is a conventional chip-scale package of the wire type. As shown in the drawing, the general shape of the chip-scale package 101xe2x80x2 of the wire type remains the same as that described for the lead-type package 100xe2x80x2, but the circuit patterns of the substrate 10xe2x80x2 of this package 101xe2x80x2 do not have leads 13 like the package 100xe2x80x2, and are electrically connected to the signal input/output pads 41xe2x80x2 of the chip 40xe2x80x2 using a-plurality of bonding wires 50xe2x80x2 in place of the leads 13xe2x80x2. Further explanation for the-wire-type package 101xe2x80x2 is thus not deemed necessary.
In the above-mentioned packages 100xe2x80x2 and 101xe2x80x2, the signal input/output terminals, or the solder balls 70, are only arranged on a limited area above the top surface of the chip 40xe2x80x2. That is, the solder ball area of each of the packages 100xe2x80x2 and 101xe2x80x2 is limited, and so such a package 100xe2x80x2, 101xe2x80x2 is called a package of the xe2x80x9cfan-inxe2x80x9d type in the art. Therefore, such a chip-scale package 100xe2x80x2, 101xe2x80x2 of the fan-in type fails to effectively meet the recent trends of compactness and smallness of the semiconductor packages or of a remarkable increase in the number of signal input/output terminals of packages. That is, since the solder ball area of the package of the fan-in type is limited, it is almost impossible for such a package to carry a desired number of solder balls within the limited solder ball area. This finally limits the designing flexibility of the chip-scale semiconductor packages.
In an effort to solve the above-mentioned problem, the outside edge of the substrate 10xe2x80x2 may be designed to further extend outwardly until the substrate 10xe2x80x2 exceeds the edge of the chip 40, thus forming an exterior area for carrying additional solder balls 70xe2x80x2 thereon. However, since a flexible substrate 10xe2x80x2 is used in the conventional packages 100xe2x80x2 and 101xe2x80x2 as described above, such an exterior area of the substrate 10xe2x80x2, exceeding the edge of the chip 40xe2x80x2, may be bent downwardly. In such a case, it is almost impossible to weld any solder ball 70xe2x80x2 to a solder ball land 15xe2x80x2 provided on the exterior area of the substrate 10xe2x80x2. Even if a solder ball 70xe2x80x2 is welded to a solder ball land 15xe2x80x2 on such an exterior area of the substrate 10xe2x80x2 with difficulty, the solder balls 70xe2x80x2 of a package 100xe2x80x2, 101xe2x80x2 may fail to accomplish a desired horizontally since the flexible substrate 10 is bent at said exterior area.
In the chip-scale package 100xe2x80x2 of the lead type shown in FIG. 11, the leads of the circuit substrate are directly bonded to the signal input/output pads or the edge pads of the semiconductor chip through a tape automated bonding process. However, an excessive bonding force is applied to the semiconductor chip during such a tape automated bonding process, thus sometimes damaging or breaking the chip. In addition, the leads of the substrate of the above package 100xe2x80x2 are designed to be thick and wide. Such thick and wide leads regrettably limit the designing flexibility of the remaining parts of the circuit patterns, or the connectors 14xe2x80x2 and the solder ball lands 15xe2x80x2, of the packages 100xe2x80x2.
The above-mentioned semiconductor packages 100xe2x80x2 and 101xe2x80x2 may be produced as follows. In order to produce such a package 100xe2x80x2, 101xe2x80x2, a wafer-shaped circuit substrate is primarily prepared. Thereafter, the wafer-shaped substrate is attached to a wafer, having a plurality of semiconductor chip units, using an-adhesive layer. This step is so-called a wafer lamination step in the art. After the wafer lamination step is accomplished, a wire/lead bonding step is performed. In the wire/lead bonding step, each signal input/output pad of each of the semiconductor chip units of the wafer is electrically connected to an associated bond finger of the substrate through a bonding process using a lead or a wire. The lead/wire bonding step is followed by a packaging step wherein the opposite upper edges or a square upper edge of each of the semiconductor chip units are individually packaged with a packaging part. The objective of the above packaging part is to protect the lead/wire bonding part, comprising the signal input/output pads and the leads or wires, from the atmospheric environment. Thereafter, a solder ball welding step, wherein a plurality of solder balls, or the signal input/output terminals of a package, are welded to the solder ball lands of the substrate, is performed. A singulation step follows the solder ball welding step. In the singulation steps the wafer-shaped substrate, integrated with the semiconductor chip units, is divided-into a plurality of semiconductor packages through a sawing process.
However, the above-mentioned method of manufacturing the chip-scale packages is problematic as follows. That is, the method produces the semiconductor packages through a wafer batch process wherein a wafer, having a plurality of chip units, is attached to a wafer-shaped substrate prior to orderly and continuously performing a lead/wire bonding step, a solder ball welding step, a packaging step, and a singulation step. In such a wafer batch process, there is no means for picking out defective chip units from the wafer prior to attaching the wafer to the substrate. Therefore, the expensive substrate, having a good quality, is regrettably wasted due to such defective chip units occupying a substantial area of the substrate in the same manner as occupied by good chip units. The conventional method of manufacturing the chip-scale packages thus results in a low production yield, reduces the productivity of the packages, and increases the manufacturing cost of the packages.
Another problem, experienced in the conventional chip-scale semiconductor packages, resides in that the packages fail to effectively dissipate heat from the semiconductor chip into the atmosphere during an operation of a package. That is, in accordance with the recent trend of high integration degree and high operational frequency of semiconductor chips, each semiconductor chip emits a large quantity of heat during an operation of a semiconductor package. However, the conventional chip-scale semiconductor packages are not designed to effectively dissipate such heat to the atmosphere, thus being reduced in electric performance and causing an operational error of the chip. This may finally reduce the operational reliability of electronic equipment using such packages. In the conventional chip-scale semiconductor packages, an interfacial separation may be formed at the junction between the parts of a package, thus sometimes undesirably separating the parts from each other or forming a crack on the chip.
Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and a primary object of the present invention is to provide a chip-scale semiconductor package of the fan-out type, which has a simple construction with the circuit substrate being designed to be stiff enough to effectively carry an increased number of solder balls, or the signal input/output terminals of the package, on its exterior area outside the edge of a semiconductor chip in addition to the area above the chip, and which thus accomplishes the recent trend of compactness, smallness, high integration degree and high operational frequency of semiconductor chips.
It is a second object of the present invention to provide a chip-scale semiconductor package of the fan-out type, of which the circuit substrate is made of a stiff or flexible material and extends outside the edge of the chip, thus forming an exterior area, with a. desired stiffness of the exterior area of the substrate being accomplished by a packaging part molded at a portion defined by the lower surface of said exterior area and the sidewall of the chip, and which thus effectively carries an increased number of solder balls and accomplishes the recent trend of compactness, smallness, high integration degree and high operational frequency of semiconductor chips.
It is a third object of the present invention to provide a chip-scale semiconductor package of the fan-out type, of which the circuit substrate is made of a stiff or flexible material and extends outside the edge of the chip, thus forming an exterior area, with a desired stiffness of the exterior area of the substrate being accomplished by a stiffener attached to the lower surface of said exterior area, thus effectively carrying an increased number of solder balls and accomplishing the recent trend of compactness, smallness, high integration degree and high operational frequency of semiconductor chips, and which also effectively dissipates heat from the chip to the atmosphere and protects the chip from unexpected external impact.
It is a fourth object of the present invention to provide a chip-scale semiconductor package of the fan-out type, of which the circuit substrate is made of a stiff or flexible material and extends outside the edge of the chip, thus forming an exterior area, with a desired stiffness of the exterior area of the substrate being accomplished by a stiffener attached to the lower surface of the exterior area of the substrate, thus effectively carrying an increased number of solder balls and accomplishing the recent trend of compactness, smallness, high integration degree and high operational frequency of semiconductor chips, and which also has a heat dissipating and protection lid on the lower surface of the chip, thus effectively dissipating heat from the chip to the atmosphere and protecting the chip from unexpected external impact.
It is a fifth object of the present invention to provide a method of manufacturing a chip-scale semiconductor package of the fan-out type, in which good quality chip units are picked out from a wafer by sawing the wafer and are attached to the lower surface of a wafer-shaped or strip-shaped circuit substrate prior to performing next steps, and which thus almost completely prevents defective chip units from being attached to the substrate, thereby improving production yield of the packages and reducing the manufacturing cost of the packages.